//==============================================================================
// Copyright (C) 2023, Advanced Micro Devices, Inc. All rights reserved.
// SPDX-License-Identifier: MIT
//
//==============================================================================

#ifndef _RN_REGISTERS_H_
#define _RN_REGISTERS_H_

/* RecoNIC register space declaration */

/* Packet Classification register space 0x100000 - 0x102FFF
 *   -- register space for sdnet table control (not used): 0x100000 - 0x101FFF
 *   -- register space for statistics and configuration: 0x102000 - 0x102FFF
 */
#define RN_PC_BASE_ADDRESS 0x100000
#define RN_SCR_OFFSET      0x2000
#define RN_CLR_OFFSET      0x3000

// PCIe bar2 and bar4 map size: 4MB and 256MB, respectively
//#define RN_SCR_MAP_SIZE  0x01000000
#define RN_SCR_MAP_SIZE  0x00400000
#define RN_RDMA_MAP_SIZE 0x10000000

/* Statistics and configuration register (SCR) space - 0x2000 - 0x2FFF */
// Read-only register
#define RN_SCR_VERSION                RN_PC_BASE_ADDRESS + RN_SCR_OFFSET + 0x0
#define RN_SCR_FATAL_ERR              RN_PC_BASE_ADDRESS + RN_SCR_OFFSET + 0x4
#define RN_SCR_TRMHR_REG              RN_PC_BASE_ADDRESS + RN_SCR_OFFSET + 0x8
#define RN_SCR_TRMLR_REG              RN_PC_BASE_ADDRESS + RN_SCR_OFFSET + 0xC
#define RN_SCR_TRRMHR_REG             RN_PC_BASE_ADDRESS + RN_SCR_OFFSET + 0x10
#define RN_SCR_TRRMLR_REG             RN_PC_BASE_ADDRESS + RN_SCR_OFFSET + 0x14
#define RN_SCR_TEMPLATE_REG           RN_PC_BASE_ADDRESS + RN_SCR_OFFSET + 0x200

/* Compute Logic register (clr) space - 0x3000 - 0x3FFF */
#define RN_CLR_CTL_CMD                RN_PC_BASE_ADDRESS + RN_CLR_OFFSET + 0x0
#define RN_CLR_KER_STS                RN_PC_BASE_ADDRESS + RN_CLR_OFFSET + 0x4
#define RN_CLR_JOB_SUBMITTED          RN_PC_BASE_ADDRESS + RN_CLR_OFFSET + 0x8
#define RN_CLR_JOB_COMPLETED_NOT_READ RN_PC_BASE_ADDRESS + RN_CLR_OFFSET + 0xC
// For testing purpose
#define RN_CLR_TEMPLATE               RN_PC_BASE_ADDRESS + RN_CLR_OFFSET + 0x200

/* ERNIC register space - 0x40000 - 0x6FFFF */
// ERNIC global control status registers (GCSR)
#define RN_RDMA_BASE_ADDRESS         0x00040000
#define RN_RDMA_GCSR_XRNICCONF       RN_RDMA_BASE_ADDRESS + 0x00020000
#define RN_RDMA_GCSR_XRNICADCONF     RN_RDMA_BASE_ADDRESS + 0x00020004
#define RN_RDMA_GCSR_MACXADDLSB      RN_RDMA_BASE_ADDRESS + 0x00020010
#define RN_RDMA_GCSR_MACXADDMSB      RN_RDMA_BASE_ADDRESS + 0x00020014
#define RN_RDMA_GCSR_IPV6XADD1       RN_RDMA_BASE_ADDRESS + 0x00020020
#define RN_RDMA_GCSR_IPV6XADD2       RN_RDMA_BASE_ADDRESS + 0x00020024
#define RN_RDMA_GCSR_IPV6XADD3       RN_RDMA_BASE_ADDRESS + 0x00020028
#define RN_RDMA_GCSR_IPV6XADD4       RN_RDMA_BASE_ADDRESS + 0x0002002C
#define RN_RDMA_GCSR_IPV4XADD        RN_RDMA_BASE_ADDRESS + 0x00020070
#define RN_RDMA_GCSR_ERRBUFBA        RN_RDMA_BASE_ADDRESS + 0x00020060
#define RN_RDMA_GCSR_ERRBUFBAMSB     RN_RDMA_BASE_ADDRESS + 0x00020064
#define RN_RDMA_GCSR_ERRBUFSZ        RN_RDMA_BASE_ADDRESS + 0x00020068
#define RN_RDMA_GCSR_IPKTERRQBA      RN_RDMA_BASE_ADDRESS + 0x00020088
#define RN_RDMA_GCSR_IPKTERRQBAMSB   RN_RDMA_BASE_ADDRESS + 0x0002008C
#define RN_RDMA_GCSR_IPKTERRQSZ      RN_RDMA_BASE_ADDRESS + 0x00020090
#define RN_RDMA_GCSR_DATBUFBA        RN_RDMA_BASE_ADDRESS + 0x000200A0
#define RN_RDMA_GCSR_DATBUFBAMSB     RN_RDMA_BASE_ADDRESS + 0x000200A4
#define RN_RDMA_GCSR_DATBUFSZ        RN_RDMA_BASE_ADDRESS + 0x000200A8
#define RN_RDMA_GCSR_INSRRPKTCNT     RN_RDMA_BASE_ADDRESS + 0x00020100  
#define RN_RDMA_GCSR_INAMPKTCNT      RN_RDMA_BASE_ADDRESS + 0x00020104
#define RN_RDMA_GCSR_OUTIOPKTCNT     RN_RDMA_BASE_ADDRESS + 0x00020108
#define RN_RDMA_GCSR_INTEN           RN_RDMA_BASE_ADDRESS + 0x00020180
#define RN_RDMA_GCSR_OUTAMPKTCNT     RN_RDMA_BASE_ADDRESS + 0x0002010C
#define RN_RDMA_GCSR_OUTNAKPKTCNT    RN_RDMA_BASE_ADDRESS + 0x00020138
#define RN_RDMA_GCSR_OUTRDRSPPKTCNT  RN_RDMA_BASE_ADDRESS + 0x0002017C
#define RN_RDMA_GCSR_RESPERRPKTBA    RN_RDMA_BASE_ADDRESS + 0x000200B0
#define RN_RDMA_GCSR_RESPERRPKTBAMSB RN_RDMA_BASE_ADDRESS + 0x000200B4
#define RN_RDMA_GCSR_RESPERRSZ       RN_RDMA_BASE_ADDRESS + 0x000200B8
#define RN_RDMA_GCSR_RESPERRSZMSB    RN_RDMA_BASE_ADDRESS + 0x000200BC
#define RN_RDMA_GCSR_STATCURSQPTRi   RN_RDMA_BASE_ADDRESS + 0x0002028C
#define RN_RDMA_GCSR_STATMSN         RN_RDMA_BASE_ADDRESS + 0x00020284

// ERNIC protection domain table registers (PDT)
#define RN_RDMA_PDT_PDPDNUM          RN_RDMA_BASE_ADDRESS + 0x00000000
#define RN_RDMA_PDT_VIRTADDRLSB      RN_RDMA_BASE_ADDRESS + 0x00000004
#define RN_RDMA_PDT_VIRTADDRMSB      RN_RDMA_BASE_ADDRESS + 0x00000008
#define RN_RDMA_PDT_BUFBASEADDRLSB   RN_RDMA_BASE_ADDRESS + 0x0000000C
#define RN_RDMA_PDT_BUFBASEADDRMSB   RN_RDMA_BASE_ADDRESS + 0x00000010
#define RN_RDMA_PDT_BUFRKEY          RN_RDMA_BASE_ADDRESS + 0x00000014
#define RN_RDMA_PDT_WRRDBUFLEN       RN_RDMA_BASE_ADDRESS + 0x00000018
#define RN_RDMA_PDT_ACCESSDESC       RN_RDMA_BASE_ADDRESS + 0x0000001C

// ERNIC per-queue control status registers (QCSR)
#define RN_RDMA_QCSR_QPCONFi         RN_RDMA_BASE_ADDRESS + 0x00020200
#define RN_RDMA_QCSR_QPADVCONFi      RN_RDMA_BASE_ADDRESS + 0x00020204
#define RN_RDMA_QCSR_RQBAi           RN_RDMA_BASE_ADDRESS + 0x00020208
#define RN_RDMA_QCSR_RQBAMSBi        RN_RDMA_BASE_ADDRESS + 0x000202C0
#define RN_RDMA_QCSR_SQBAi           RN_RDMA_BASE_ADDRESS + 0x00020210
#define RN_RDMA_QCSR_SQBAMSBi        RN_RDMA_BASE_ADDRESS + 0x000202C8
#define RN_RDMA_QCSR_CQBAi           RN_RDMA_BASE_ADDRESS + 0x00020218
#define RN_RDMA_QCSR_CQBAMSBi        RN_RDMA_BASE_ADDRESS + 0x000202D0
#define RN_RDMA_QCSR_RQWPTRDBADDi    RN_RDMA_BASE_ADDRESS + 0x00020220
#define RN_RDMA_QCSR_RQWPTRDBADDMSBi RN_RDMA_BASE_ADDRESS + 0x00020224
#define RN_RDMA_QCSR_CQDBADDi        RN_RDMA_BASE_ADDRESS + 0x00020228
#define RN_RDMA_QCSR_CQDBADDMSBi     RN_RDMA_BASE_ADDRESS + 0x0002022C
#define RN_RDMA_QCSR_CQHEADi         RN_RDMA_BASE_ADDRESS + 0x00020230
#define RN_RDMA_QCSR_RQCIi           RN_RDMA_BASE_ADDRESS + 0x00020234
#define RN_RDMA_QCSR_SQPIi           RN_RDMA_BASE_ADDRESS + 0x00020238
#define RN_RDMA_QCSR_QDEPTHi         RN_RDMA_BASE_ADDRESS + 0x0002023C
#define RN_RDMA_QCSR_SQPSNi          RN_RDMA_BASE_ADDRESS + 0x00020240
#define RN_RDMA_QCSR_LSTRQREQi       RN_RDMA_BASE_ADDRESS + 0x00020244
#define RN_RDMA_QCSR_DESTQPCONFi     RN_RDMA_BASE_ADDRESS + 0x00020248
#define RN_RDMA_QCSR_MACDESADDLSBi   RN_RDMA_BASE_ADDRESS + 0x00020250
#define RN_RDMA_QCSR_MACDESADDMSBi   RN_RDMA_BASE_ADDRESS + 0x00020254
#define RN_RDMA_QCSR_IPDESADDR1i     RN_RDMA_BASE_ADDRESS + 0x00020260
#define RN_RDMA_QCSR_IPDESADDR2i     RN_RDMA_BASE_ADDRESS + 0x00020264
#define RN_RDMA_QCSR_IPDESADDR3i     RN_RDMA_BASE_ADDRESS + 0x00020268
#define RN_RDMA_QCSR_IPDESADDR4i     RN_RDMA_BASE_ADDRESS + 0x0002026C
#define RN_RDMA_QCSR_STATMSNi        RN_RDMA_BASE_ADDRESS + 0x00020284
#define RN_RDMA_QCSR_STATQPi         RN_RDMA_BASE_ADDRESS + 0x00020288
#define RN_RDMA_QCSR_STATRQPIDBi     RN_RDMA_BASE_ADDRESS + 0x0002029C
#define RN_RDMA_QCSR_PDi             RN_RDMA_BASE_ADDRESS + 0x000202B0

// WQE opcode: 8-bit
#define RNIC_OP_WRITE        0
#define RNIC_OP_WRITE_IMMDT  1
#define RNIC_OP_SEND         2
#define RNIC_OP_SEND_IMMDT   3
#define RNIC_OP_READ         4
#define RNIC_OP_SEND_INV     12

// QDMA AXI Bridge mapping and configuration
#define RN_QDMA_CSR_BASE_ADDRESS 0x00014000
#define AXIB_BDF_ADDR_TRANSLATE_ADDR_LSB RN_QDMA_CSR_BASE_ADDRESS + 0x00002420
#define AXIB_BDF_ADDR_TRANSLATE_ADDR_MSB RN_QDMA_CSR_BASE_ADDRESS + 0x00002424
#define AXIB_BDF_PASID_RESERVED_ADDR     RN_QDMA_CSR_BASE_ADDRESS + 0x00002428
// function number is 12-bit
#define AXIB_BDF_FUNCTION_NUM_ADDR       RN_QDMA_CSR_BASE_ADDRESS + 0x0000242C
// Map control:
// - [31:30] Read/Write Access permission, set to 2'b11
// - [29] : R0 access Error, set to 1'b0
// - [28:26] Protection ID, set to 3'd0
// - [25:0] Window Size in unit of 4K. we use 256MB mapping, so set it to 65536
#define AXIB_BDF_MAP_CONTROL_ADDR        RN_QDMA_CSR_BASE_ADDRESS + 0x00002430
#define AXIB_BDF_RESERVED_ADDR           RN_QDMA_CSR_BASE_ADDRESS + 0x00002434
//#define AXIB_BDF_MAP_CONTROL             0xC0010000 
#define AXIB_BDF_MAP_CONTROL             0xC4000000 

#endif  /* _RN_REGISTERS_H_ */